1. Field of Use
The present invention relates to memory arrays, and more particularly to memory arrays using settable threshold memory cells.
2. Description of Related Art
Various memory arrays have been developed using various types of settable threshold memory cells. For example, one conventional type of array, which is described in FIG. 5a of Mukherjee et al. U.S. Pat. No. 4,698,787, issued Oct. 6, 1987, uses a two transistor electrically erasable programmable read only memory ("E.sup.2 PROM") cell. One transistor of this cell is a select transistor. The other transistor of this cell is a floating gate transistor in which Fowler-Nordheim tunneling is used to transport charge to or from the floating gate for storing a binary value by selectively setting the transistor to either a low threshold voltage ("V.sub.t ") state or a high V, state. The charge is transported through a tunnel dielectric insulating the transistor drain from the floating gate. As various conventions appear in the literature for the terms "erase" and "program," the terms low V.sub.t and high V.sub.t are used herein when generally referring to the state of a memory cell. Typically, about twenty volts is needed to alter the V.sub.t state of the transistor. In a typical E.sup.2 PROM memory array, initially all cells of the cell array are placed into a high V.sub.t state by grounding the drain and pulsing the gate at a potential of about plus twenty volts. Then, the desired logic value is written into the array by placing selected cells into a low V.sub.t state by grounding the gate and pulsing the drain of the selected cells at a potential of about plus twenty volts. The select transistor, then, is used for the purposes of: (1) isolating deselected cells from selected cells while the bit lines are pulsed to set low V.sub.t ; and (2) isolating deselected cells from selected cells during memory read operations, which prevents deselected cells that were written into depletion from drawing current from the bit lines to give a false state indication. Unfortunately, a cell array based on the two transistor cell consumes considerable space on the die because of the size of the two transistor cell, thereby seriously limiting the size of an integrated circuit memory.
Various memory cell arrays have been proposed that are not based on the two transistor cell. For example, Nakayama et al. U.S. Pat. No. 4,903,236, issued Feb. 20, 1990, discloses an array in FIG. 5 that uses a particular combination of high voltages on the word and bit lines purportedly to avoid the need for a two transistor cell, even though a two transistor cell is preferred.
The previously mentioned Mukherjee et al. patent discloses in FIG. 5b another array based on a single asymmetrical source/drain E.sup.2 PROM memory cell that is placed into a high V.sub.t state using hot electrons in a manner similar to conventional EPROM transistors, and placed into a low V.sub.t state in a manner similar to a conventional E.sup.2 PROM cell except that the tunnel dielectric is located between the source and the floating gate. In this array, initially all cells of the array are placed in a low V.sub.t state by grounding the word lines and pulsing the common source line. A byte erase scheme is also proposed in FIG. 5d of Mukherjee et al. that incorporates an additional transistor for each word. Cells are placed in a high V.sub.t state by channel hot electron injection into the floating gate, which is achieved by (a) grounding the common source line, raising the drain voltage of the selected cells, and pulsing the gate of the selected cells with positive voltage. Channel hot electron injection occurs in only selected cells having a raised drain voltage. Selected cells having a grounded drain do not assume a high V.sub.t state since they lack channel hot electron generation, and deselected cells do not assume a high V.sub.t state since they lack hot electron transport.
The memory cell used in the Mukherjee et al. array is a type of E.sup.2 PROM cell commonly known as flash memory. Flash memory technology as it is generally referred to involves channel hot electron injection to achieve the high V.sub.t state, and Fowler-Nordheim tunneling to achieve the low V.sub.t state. Flash memory is described in further detail in K. Robinson, "Endurance Brightens the Future of Flash," Electronic Component News, November 1988.
As generally envisioned, flash memory cells are single transistors cells. A flash memory avoids over-erasure of its cells into depletion by using a complex and time consuming software-implemented technique. For example, to write a byte of data into a flash memory, a block of the flash memory is selected, preconditioned, erased, and entirely rewritten. This process can take hundreds of milliseconds. See R. Wilson and D. Lammers, "Intel flash prices rock market," Electronic Engineering Times, Apr. 27, 1992, p. 92-93.
Flash memory typically has several disadvantages. Because of the techniques generally used to prevent individual cells from over-erasing into depletion, a write operation is cumbersome and time-consuming, requiring typically hundreds of milliseconds. Because setting the high V.sub.t state relies on channel hot electron injection, each memory cell being set into the high V.sub.t state draws considerable current, typically as much as a milliampere. The high power consumption limits, as a practical matter, the number of cells that can be set into the high V.sub.t state at a time. Typically, the limit is eight cells. Moreover, the voltage required for setting the memory cells in a high V.sub.t state must be obtained from an external source because of the power requirement.
A flash memory cell has been developed that use Fowler-Nordheim tunnelling for both programming and erasure; see Gill et al., "A 5-Volt Contactless Array 256 Kbit FLASH EEPROM Technology," Proceedings IEDM, 1988, pp. 428-431. The cell is operated using a particular combination of voltages on the word and bit lines. The cell includes an integral pass gate, since it is used in a memory architecture in which cells erased into depletion are problematic. Although the cell is somewhat smaller due to its use of an integral pass gate, nonetheless the cell is larger and more complicated than a conventional flash cell.